In the fabrication of vertical field effect transistors (VFETs) it is common to form gate areas by implanting or otherwise doping a substrate or epitaxial layer on the substrate. The doped areas or implanted areas must then be activated by a relatively high annealing temperature. The annealing temperature is high enough to cause major problems with any ohmic metal that has been previously deposited on the substrate. For example, most of the ohmic metals contain gold and annealing temperatures will cause gold to diffuse into the substrate and produce a very bad ohmic contact.
Thus, in prior art VFETs it is necessary to do all doping and annealing prior to the deposition of ohmic contacts. Any source or gate positioning must be accomplished through very careful alignment, which adds greatly to the cost and substantially reduces reliability. Further, since the deposition of metal contacts is one of the last steps to be performed, no probing of the prior art VFETs can be performed prior to completion. This again adds unduly to the cost, since early difficulties in the process cannot be detected.
It would be highly advantageous to provide a manufacturable GaAs VFET process which overcomes these drawbacks.
It is a purpose of the present invention to provide a new and improved manufacturable GaAs VFET process.
It is another purpose of the present invention to provide a new and improved manufacturable GaAs VFET process which allows the use of ohmic contacts prior to implant and activation steps.
It is still another purpose of the present invention to provide a new and improved manufacturable GaAs VFET process which allows the use of source metal as a self-aligned etch and implant mask.
It is a further purpose of the present invention to provide a new and improved manufacturable GaAs VFET process which allows testing of the VFETs at intermediate points in the process.